CMOS Image Sensor Featuring Current-Mode Focal-Plane Image Compression

The main feature of CMOS image sensors is that they allow for the introduction of processing hardware at the pixel level. Using this characteristic, it is possible to extract from the image only the desired data, thereby reducing the output data rate. The analog processing also has the advantage of enabling high-speed operation. Owing to these features, in the last few years there has been a strong interest in CMOS image sensors, called here as imagers [1]-[8]. The imager described in this paper is capable of compressing a gray scale image using analog hardware [9]. The compression is lossy and the method used, which is based on DPCM (differential pulse-code modulation) and VQ (vector quantization), is briefly reviewed in Section II. To decode the bits produced by the chip, we use the decoder described in Section III. The pseudo-code necessary to generate the image is also shown in this section. Other experimental results from the chip can be found in [10], [11]. The main purpose of this paper is to report theoretical and experimental results that show the contributions of the DPCM and VQ analog circuits in producing the pictures taken by the chip. The pseudo-code in Section III describes the theoretical contributions and shows how the DPCM and VQ results are put together to create the final image. Section IV briefly describes the circuits that are used for the implementation of the DPCM algorithm. Experimental results are presented in Section V, and concluding remarks are made in Section VI.